1. Field of the Invention
The present invention generally relates to serial data bus communication systems and in particular to delay line separators for extracting a clock signal from a combined clock/data encoded input signal received from a serial data bus line.
2. Description of Related Art
Serial backplane data bus systems for transmitting data from one computer to another, or from one computer to a peripheral, often employ only a single communication line. With a single data line transmission, clock information and data information are combined in single packets of information. To accurately extract the data from the signal, the receiving bus system must be capable of first extracting a clock signal from the combined signal. Once the clock signal is extracted, the clock signal is used to sample the received signal to extract data.
A variety of conventional encoding schemes are employed to send combined clock and data transmissions over a single data line. Examples are Manchester, 4B5B and 8B10B. Transmissions encoded in, for example, binary 4B5B encodes 4 bits of data in 5 NRZ binary symbols. The purpose of the encoding is to guarantee both a dc balanced signal and enough transitions for clock extraction circuits to be able to extract the clock. A typical sequence of symbols within a transmitted signal is shown in FIG. 1. As can be seen, each symbol of the transmitted signal fills a bit cell, for 40 megabit 4B5B data, the symbol rate is 50 Mbaud and the bit cell is 20 nanoseconds.
To decode the 4B5B packet to extract the transmitted data, a clock signal encoded within the data packet must first be extracted. A wide variety of techniques has been developed for determining the bit cell width of a received packet of information to determine the clock frequency, as well as the clock signal starting point. One typical technique employs a phase-lock loop for extracting the clock from the received packet. Although a phase-lock loop technique is effective for certain types of serial data bus transmissions, a phase-lock loop is not effective for a data bus that transmits data in short packets (burst mode) followed by long periods of idle in which no clock is present, such as IEEE 1394 Serial Bus. A phase-lock loop is ineffective because the phase-lock loop requires considerable time to acquire a lock on an incoming signal. Thus, with short high speed data bursts, a substantial portion of an input packet of information may be lost merely acquiring a phase lock before any data can be read. Moreover phase-lock loop techniques are analog closed-loop architectures which can have instabilities and noise problems.
In view of these disadvantages to phase-lock loop techniques, modern serial data bus receivers employ other techniques for extracting a clock signal from a combined clock/data input packet. One alternative technique employs a delay line which includes a series of delay elements arranged in series, each receiving a portion of the received packet of data.
A number of different types of noise or distortion can affect a packet as it is transmitted over a serial data bus. Of particular interest to short range, high speed data burst transmissions is a systematic distortion which uniformly varies the duty cycle of the symbols within the data packet. Referring again to FIG. 1, a symbol within a transmitted signal is bounded by a rising edge and a sharp falling edge and has a width equal to the bit cell, typically 20 nanoseconds for 50 Mbaud 4B5B. However, during transmission of the packet, a pulse corresponding to a single symbol is broadened or narrowed, such that the time between a rising edge and a succeeding falling edge is increased or decreased. Such a systematic error is represented in FIG. 1 by the received signal, which includes rising edges advanced by one or two nanoseconds and falling edges delayed by one or two nanoseconds. With such distortion, each high symbol is broadened and spacing between high symbols is decreased. Thus, whereas the bit cell width of the transmitted signal is easily determined from the time between rising and falling edges, the bit cell width cannot be easily determined from the time between rising and falling edges of the received signal. Although shown as broadening each signal, systematic distortion of the kind described can also narrow each symbol, thus broadening spacing between low symbols. The amount of broadening or narrowing of symbols can be quite significant, often resulting in an initial 20 nanosecond symbol being expanded to a width of 30 nanoseconds or narrowed to a width of 10 nanoseconds.
A unique feature of the systematic distortion is that the distance between successive rising edges is unaffected by the distortion. This is true because the source of the distortion affects each symbol pulse in the same manner and by the same amount such that all rising edges are advanced or delayed by a certain amount and all falling edges are advanced or delayed by a certain amount. Such systematic distortion is commonly referred to as duty-cycle distortion and may arise from a rise/fall time mismatch or from offsets in the receiver. Other types of distortion, which do not preserve the time between successive rising edges, include external noise, transient noise and inter-symbol interference. However, during transmission and reception of the packet, the symbol pulse widths are distorted such that high symbol pulse widths are increased (decreased) while low symbol pulse widths are correspondingly decreased (increased) by the same amount. This distortion may vary from packet to packet but does not vary during a packet transmission. The amount of broadening and narrowing of the symbols can be quite significant, often resulting in an initial 20 nanosecond symbol bit cell being expanded to a width of 30 nanoseconds while the opposite value symbol is decreased to 10 nanoseconds.
Heretofore, no effective delay line techniques have been developed which allow the extraction of a clock signal from a high speed clock/data burst in the presence of significant duty-cycle distortion. Techniques which have addressed the problem are either not sufficiently effective in extracting the clock signal or are complex, thus rendering the system expensive.